LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY BufferRegister_8_Byte IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		load		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END BufferRegister_8_Byte;

ARCHITECTURE SYN OF BufferRegister_8_Byte IS

	SIGNAL reg0_output	: 	STD_LOGIC_VECTOR (7 DOWNTO 0);

	COMPONENT BufferRegister_4_Byte IS
		PORT
		(
			aclr		: IN STD_LOGIC ;
			clock		: IN STD_LOGIC ;
			data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			load		: IN STD_LOGIC ;
			q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
	END COMPONENT BufferRegister_4_Byte;

BEGIN
	
	reg0: BufferRegister_4_Byte PORT MAP  (aclr, clock, data, load, reg0_output);
	reg1: BufferRegister_4_Byte PORT MAP  (aclr, clock, reg0_output, load, q);
	
END SYN;